In conventional memory applications, a number of memory address/control signals and a memory clock signal are generated from a memory controller. Such an implementation is particularly true for a double data rate (DDR) memory. The control and clock signals have certain skew parameters according to the particular memory specification. One conventional approach to controlling skew timing is to use a single speed (i.e., 1×) clock signal to generate the memory address/control signals and to use a double speed (i.e., 2×) clock signal to generate a clock signal for the memory. Since such an approach involves two different clock domains, a system for balancing the clock skew between the two clock domains is needed. Such balancing increases the complexity and/or reduces reliability of such a design.
It would be desirable to implement a memory interface that maximizes an access timing margin by using a single external clock signal.